From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/i915/psr: Program Panel Replay CONFIG3 using AS SDP transmission time Date: Tue, 31 Mar 2026 17:39:48 +1000 Message-ID: In-Reply-To: <20260330040656.4116502-16-ankit.k.nautiyal@intel.com> References: <20260330040656.4116502-1-ankit.k.nautiyal@intel.com> <20260330040656.4116502-16-ankit.k.nautiyal@intel.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Patch Review **Critical concern:** This extends the `panel_replay_config` array from 2 t= o 3 bytes and writes all 3 starting at `PANEL_REPLAY_CONFIG` (0x1b0). This = means byte [2] goes to address 0x1b2. But patch 4 defines `PANEL_REPLAY_CON= FIG3` at address **0x11a**, not 0x1b2. These are inconsistent =E2=80=94 eit= her the CONFIG3 address is wrong or this burst write is wrong. If PANEL_REPLAY_CONFIG3 is truly at 0x11a, then this burst write writes to = the wrong address. If it should be at 0x1b2, then patch 4's definition is w= rong. --- Generated by Claude Code Patch Reviewer