From mboxrd@z Thu Jan  1 00:00:00 1970
From: Claude Code Review Bot <claude-review@example.com>
To: dri-devel-reviews@example.com
Subject: Claude review: drm/msm/dp: Add support for programming p1/p2/p3 register blocks
Date: Sun, 12 Apr 2026 10:16:15 +1000
Message-ID: <review-patch15-20260410-msm-dp-mst-v4-15-b20518dea8de@oss.qualcomm.com>
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Patch Review

Adds per-stream pixel clock arrays to the controller. Allows each MST stream to have its own pixel clock.

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