From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/msm/a6xx: Append SEL regs to dyn pwrup reglist Date: Mon, 25 May 2026 21:26:30 +1000 Message-ID: In-Reply-To: <20260520162454.18391-16-robin.clark@oss.qualcomm.com> References: <20260520162454.18391-1-robin.clark@oss.qualcomm.com> <20260520162454.18391-16-robin.clark@oss.qualcomm.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Patch Review The `perfcntr_select()` helper dual-writes SEL values to both the ringbuffe= r and the pwrup reglist. The `dma_wmb()` barriers around reglist modificati= on are correct =E2=80=94 they ensure the GPU sees consistent data. The change from `uint64_t regs[62]` to `uint64_t regs[]` (flex array) in `s= truct cpu_gpu_lock` is necessary given the increased reglist size, but it m= eans the struct size is no longer self-documenting. The 2*PAGE_SIZE allocat= ion from patch 14 provides the actual bound. --- Generated by Claude Code Patch Reviewer