From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/msm/a6xx: Append SEL regs to dyn pwrup reglist Date: Mon, 25 May 2026 18:21:42 +1000 Message-ID: In-Reply-To: <20260522173349.55491-16-robin.clark@oss.qualcomm.com> References: <20260522173349.55491-1-robin.clark@oss.qualcomm.com> <20260522173349.55491-16-robin.clark@oss.qualcomm.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Patch Review The `perfcntr_select` helper writes to both the ringbuffer and the pwrup reglist simultaneously. The reglist overflow check is a good safety guard: ```c WARN_ON_ONCE(reglist > (uint32_t *)((uint8_t *)lock + PWRUP_REGLIST_SIZE)); ``` The change from fixed `uint64_t regs[62]` to flexible `uint64_t regs[]` in `cpu_gpu_lock` is necessary to accommodate the larger reglist. The reasoning about skipping the spinlock dance with SQE is sound: if SQE reads the old (shorter) dynamic_list_len, it restores fewer regs. Then the ringbuffer programming corrects the SEL regs before any sampling begins. The barrier sequencing is correct: 1. Clear `dynamic_list_len` to remove old SEL entries 2. `dma_wmb()` -- GPU sees shorter list before we modify the data 3. Write new SEL entries 4. `dma_wmb()` -- GPU sees new data before longer length 5. Update `dynamic_list_len` to include new SEL entries --- Generated by Claude Code Patch Reviewer