From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/msm/a6xx: Allow IFPC with perfcntr stream Date: Mon, 25 May 2026 18:21:42 +1000 Message-ID: In-Reply-To: <20260522173349.55491-17-robin.clark@oss.qualcomm.com> References: <20260522173349.55491-1-robin.clark@oss.qualcomm.com> <20260522173349.55491-17-robin.clark@oss.qualcomm.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Patch Review Changes `sysprof_setup` to accept `bool force_on` and calls it from `sample_worker` to inhibit IFPC only during register reads: ```c /* Inhibit IFPC while accessing registers: */ if (gpu->funcs->sysprof_setup) gpu->funcs->sysprof_setup(gpu, true); // ... read counters ... /* Re-enable IFPC: */ if (gpu->funcs->sysprof_setup) gpu->funcs->sysprof_setup(gpu, false); ``` The `msm_gpu_sysprof_no_ifpc` now only checks `sysprof_active` (legacy userspace path), not the perfcntr stream, since IFPC is now handled dynamically for streams. Clean separation. The `msm_context_set_sysprof` call is correctly updated to pass `false` for `force_on`. --- **Summary of findings:** - **One bug**: `msm_perfcntrs_stream_read` returns 0 (EOF) instead of `-EAGAIN` when `O_NONBLOCK` is set and no data is available. - The rest of the series is well-engineered with careful attention to locking, barrier ordering, and power management synchronization. --- Generated by Claude Code Patch Reviewer