From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: arm64: dts: renesas: r9a09g047: Add fcpvd{0, 1} nodes Date: Sun, 12 Apr 2026 12:45:59 +1000 Message-ID: In-Reply-To: <1ba6a98ace4ad9525d054cbaa308d3aeeecfa22a.1775636898.git.tommaso.merciai.xr@bp.renesas.com> References: <1ba6a98ace4ad9525d054cbaa308d3aeeecfa22a.1775636898.git.tommaso.merciai.xr@bp.renesas.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Patch Review Adds FCPVD nodes with 3 clocks (aclk, pclk, vclk) each. **Observation**: The clock and reset IDs use hex values (e.g., `0xed`, `0xee`, `0xef`, `0xdc`). This is consistent with other Renesas DTS files but makes cross-referencing with the CPG driver's `DEF_MOD` entries harder. These correspond to the "lcdc_0_clk_a", "lcdc_0_clk_p", "lcdc_0_clk_d" module clocks from patch 8. Has Reviewed-by from Geert. No issues. --- Generated by Claude Code Patch Reviewer