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From: Claude Code Review Bot <claude-review@example.com>
To: dri-devel-reviews@example.com
Subject: Claude review: Revert "drm/amd/pm: Disable SCLK switching on Oland with high pixel clocks (v3)"
Date: Mon, 23 Feb 2026 06:01:57 +1000	[thread overview]
Message-ID: <review-patch2-20260221034402.69537-3-rosenp@gmail.com> (raw)
In-Reply-To: <20260221034402.69537-3-rosenp@gmail.com>

Patch Review

The commit message has a reasonable explanation but has a few issues:

> In 6.17, threre are further commits that are needed to get the DC
> codepath in amdgpu for Southern Islands GPUs working but they seem to be
> too much of a hastle to backport cleanly. The simplest solution is to
> revert this problematic commit

Typos: "threre" should be "there", "hastle" should be "hassle". The last paragraph is also missing a period. Per the mailing list discussion, the commit message should also specify which stable kernels are affected (6.1.y, 6.6.y, 6.12.y) and clarify that 6.17+ already has proper fixes.

The code change removes the entire high-pixelclock counting loop and its associated logic:

> -	for (i = 0; i < adev->mode_info.num_crtc; i++) {
> -		if (!(adev->pm.dpm.new_active_crtcs & (1 << i)) ||
> -			!adev->mode_info.crtcs[i]->enabled)
> -			continue;
> -
> -		conn = to_amdgpu_connector(adev->mode_info.crtcs[i]->connector);
> -
> -		if (conn->pixelclock_for_modeset > 297000)
> -			high_pixelclock_count++;
> -	}

This is the code that causes the panic -- the `to_amdgpu_connector()` call on `adev->mode_info.crtcs[i]->connector` likely hits a NULL or invalid pointer when the DC codepath is active on SI GPUs. Removing it fixes the crash.

The patch also cleans up the now-unused variable declarations:

> -	struct amdgpu_connector *conn;
> ...
> -	u32 high_pixelclock_count = 0;

`disable_sclk_switching` remains declared and initialized to `false` but is never set to `true` after both patches. This is correct behavior -- the variable existed before the original commit and is referenced later in the function, so it must stay. It will just always be `false`, effectively disabling the SCLK switching workaround.

No correctness issues with the code change. The tradeoff (losing the flickering workaround vs. fixing a crash) is clearly the right one for stable kernels.

---
Generated by Claude Code Patch Reviewer

  parent reply	other threads:[~2026-02-22 20:01 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-02-21  3:44 [PATCH 0/2] 6.12 and below: amdgpu: fix panic with SI and DC Rosen Penev
2026-02-21  3:44 ` [PATCH 1/2] Revert "drm/amd/pm: Disable MCLK switching on SI at high pixel clocks" Rosen Penev
2026-02-21  5:40   ` Greg KH
2026-02-21  5:54     ` Rosen Penev
2026-02-21  6:33       ` Greg KH
2026-02-22 20:01   ` Claude review: " Claude Code Review Bot
2026-02-21  3:44 ` [PATCH 2/2] Revert "drm/amd/pm: Disable SCLK switching on Oland with high pixel clocks (v3)" Rosen Penev
2026-02-21  5:41   ` Greg KH
2026-02-21  5:52     ` Rosen Penev
2026-02-21  6:33       ` Greg KH
2026-02-21  8:48         ` Rosen Penev
2026-02-22 20:01   ` Claude Code Review Bot [this message]
2026-02-21  5:41 ` [PATCH 0/2] 6.12 and below: amdgpu: fix panic with SI and DC Greg KH
2026-02-21  5:55   ` Rosen Penev
2026-02-22 20:01 ` Claude review: " Claude Code Review Bot

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