Claude review: drm/bridge: ti-sn65dsi83: halve horizontal syncs for dual LVDS output

[Claude Code Review Bot <claude-review@example.com>]

Patch Review

**Verdict: Looks good, one minor style nit.**

The logic is sound. In dual LVDS mode, two pixels are output per clock cycle, so the horizontal timing values (measured in pixel clocks) need to be halved. The patch correctly divides:
- `HSYNC_PULSE_WIDTH` (`mode->hsync_end - mode->hsync_start`)
- `HORIZONTAL_BACK_PORCH` (`mode->htotal - mode->hsync_end`)
- `HORIZONTAL_FRONT_PORCH` (`mode->hsync_start - mode->hdisplay`)

Vertical timing is correctly left untouched. The division factor is neatly captured in:

```c
const unsigned int dual_factor = ctx->lvds_dual_link ? 2 : 1;
```

**Minor nit**: The variable declaration ordering places `dual_factor` between `ctx` and the `const struct` declarations. The kernel style convention historically prefers reverse-christmas-tree ordering of declarations, but this is a trivial style point and doesn't affect correctness. The `ctx->lvds_dual_link` access is safe here since `ctx` is derived from the function parameter and `lvds_dual_link` is set during probe.

One thing to note: the patch doesn't halve `SYNC_DELAY` (kept at the fixed value `32 + 1`). Based on the DSI Tuner tool reference, this appears intentional and correct.

Fixes tag and stable Cc are appropriate.

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