From: Claude Code Review Bot <claude-review@example.com>
To: dri-devel-reviews@example.com
Subject: Claude review: dt-bindings: display: msm: Fix reg ranges for DP example node
Date: Tue, 03 Mar 2026 13:37:09 +1000 [thread overview]
Message-ID: <review-patch2-20260302-glymur-fix-dp-bindings-reg-clocks-v3-2-8fe49ac1f556@oss.qualcomm.com> (raw)
In-Reply-To: <20260302-glymur-fix-dp-bindings-reg-clocks-v3-2-8fe49ac1f556@oss.qualcomm.com>
Patch Review
This patch updates the example node in `qcom,glymur-mdss.yaml` to match the new 9-entry reg constraint from patch 1. The changes look correct:
```yaml
displayport-controller@af54000 {
reg = <0xaf54000 0x200>, # ahb
<0xaf54200 0x200>, # aux
<0xaf55000 0xc00>, # link
<0xaf56000 0x400>, # p0
<0xaf57000 0x400>, # p1
<0xaf58000 0x400>, # p2
<0xaf59000 0x400>, # p3
<0xaf5a000 0x600>, # mst2link
<0xaf5b000 0x600>; # mst3link
```
- 9 reg entries, matching `minItems: 9` / `maxItems: 9` from patch 1.
- The unit address `@af54000` correctly matches the first reg entry base address.
- The commit message explains these are actual addresses from the first controller rather than made-up ones, which is good practice for binding examples.
- 6 clocks are listed in the example, which is within the 5-6 range from patch 1.
This patch is straightforward and correct. No issues beyond the dependency on patch 1's `clocks-names` typo (which would cause dtbs_check to not enforce the clock-names constraint on this example, but it also wasn't enforced before).
---
Generated by Claude Code Patch Reviewer
next prev parent reply other threads:[~2026-03-03 3:37 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-02 9:58 [PATCH v3 0/2] dt-bindings: display: msm: Fix Glymur DP controller reg ranges and clock Abel Vesa
2026-03-02 9:58 ` [PATCH v3 1/2] dt-bindings: display: msm: Fix reg ranges and clocks on Glymur Abel Vesa
2026-03-02 11:36 ` Rob Herring (Arm)
2026-03-03 3:37 ` Claude review: " Claude Code Review Bot
2026-03-02 9:58 ` [PATCH v3 2/2] dt-bindings: display: msm: Fix reg ranges for DP example node Abel Vesa
2026-03-02 13:15 ` Dmitry Baryshkov
2026-03-03 3:37 ` Claude Code Review Bot [this message]
2026-03-03 3:37 ` Claude review: dt-bindings: display: msm: Fix Glymur DP controller reg ranges and clock Claude Code Review Bot
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