From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: dt-bindings: display: msm: Fix reg ranges for DP example node Date: Tue, 03 Mar 2026 13:37:09 +1000 Message-ID: In-Reply-To: <20260302-glymur-fix-dp-bindings-reg-clocks-v3-2-8fe49ac1f556@oss.qualcomm.com> References: <20260302-glymur-fix-dp-bindings-reg-clocks-v3-0-8fe49ac1f556@oss.qualcomm.com> <20260302-glymur-fix-dp-bindings-reg-clocks-v3-2-8fe49ac1f556@oss.qualcomm.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Patch Review This patch updates the example node in `qcom,glymur-mdss.yaml` to match the new 9-entry reg constraint from patch 1. The changes look correct: ```yaml displayport-controller@af54000 { reg = <0xaf54000 0x200>, # ahb <0xaf54200 0x200>, # aux <0xaf55000 0xc00>, # link <0xaf56000 0x400>, # p0 <0xaf57000 0x400>, # p1 <0xaf58000 0x400>, # p2 <0xaf59000 0x400>, # p3 <0xaf5a000 0x600>, # mst2link <0xaf5b000 0x600>; # mst3link ``` - 9 reg entries, matching `minItems: 9` / `maxItems: 9` from patch 1. - The unit address `@af54000` correctly matches the first reg entry base address. - The commit message explains these are actual addresses from the first controller rather than made-up ones, which is good practice for binding examples. - 6 clocks are listed in the example, which is within the 5-6 range from patch 1. This patch is straightforward and correct. No issues beyond the dependency on patch 1's `clocks-names` typo (which would cause dtbs_check to not enforce the clock-names constraint on this example, but it also wasn't enforced before). --- Generated by Claude Code Patch Reviewer