From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/i915/color: Add CSC on SDR plane color pipeline Date: Mon, 09 Mar 2026 08:26:52 +1000 Message-ID: In-Reply-To: <20260306165307.3233194-3-chaitanya.kumar.borah@intel.com> References: <20260306165307.3233194-1-chaitanya.kumar.borah@intel.com> <20260306165307.3233194-3-chaitanya.kumar.borah@intel.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Patch Review Clean patch. Adds the SDR pipeline definition and routes planes correctly b= ased on `icl_is_hdr_plane`. One concern: the `sdr_plane_pipeline` initially has only `INTEL_PLANE_CB_CS= C_FF` =E2=80=94 the LUTs are added in patch 4. This means between patches 2= -3 and patch 4, the SDR pipeline would be incomplete if bisecting. Not a fu= nctional issue since patch 10 is what actually enables the pipeline for use= rspace, but the intermediate states are worth being aware of for bisection. --- Generated by Claude Code Patch Reviewer