Claude review: drm/tyr: Set interconnect coherency during probe

[Claude Code Review Bot <claude-review@example.com>]

Patch Review

This patch writes `NO_COHERENCY` to the `COHERENCY_ENABLE` register during probe, then reads it back for `GpuInfo`.

The change is sound in principle — it ensures the register is in a known state and the `GpuInfo` struct reflects reality. However:

**Potential issue with `into_raw()` for `selected_coherency`:**
```rust
selected_coherency: io.read(COHERENCY_ENABLE).into_raw(),
```
The `COHERENCY_ENABLE` register has a single field `l2_cache_protocol_select` spanning bits 31:0. Reading the full raw value should work since the field spans the whole register. But the UAPI constants (`DRM_PANTHOR_GPU_COHERENCY_NONE` = 0, `ACE_LITE` = 1, `ACE` = 2) are small values, so this should be fine.

**The `with_const_l2_cache_protocol_select` call is verbose but correct.** Writing `NO_COHERENCY` (0) to a zeroed register is effectively a no-op write, but it serves the purpose of establishing a known state.

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