Claude review: arm64: dts: qcom: talos: Add gpu and rgmu nodes

[Claude Code Review Bot <claude-review@example.com>]

Patch Review

**Issue: GMU node unit address mismatch.**

The node name is `gmu@506a000` but the `reg` property starts at `0x0506d000`:

```dts
gmu: gmu@506a000 {
    compatible = "qcom,adreno-rgmu-612.0", "qcom,adreno-rgmu";
    reg = <0x0 0x0506d000 0x0 0x2c000>;
```

Per DT conventions, the unit address in the node name must match the first address in the `reg` property. This should be `gmu@506d000`. For comparison, the full GMU on SDM845 uses `gmu@506a000` with `reg = <0 0x0506a000 ...>` — matching correctly. The RGMU on this SoC starts at a different offset and the node name must reflect that. This will likely trigger a `dtbs_check` warning (`node name unit address does not match first reg entry`).

Note: The binding document example (`qcom,adreno-rgmu.yaml` line 90–93) itself has a mismatch (`gmu@506a000` with `reg = <0x05000000 0x90000>`) — that's a pre-existing issue in the binding doc, not introduced by this series, but worth fixing as a follow-up.

**Rest of patch 2 looks good:**
- The `pil_gpu_mem` reserved memory region at `0x97715000` with size `0x2000` and `no-map` is standard for GPU firmware.
- The GPU node at `gpu@5000000` follows the established A6xx pattern with correct `reg-names` (`kgsl_3d0_reg_memory`, `cx_mem`, `cx_dbgc`).
- OPP table has 5 entries (435–845 MHz) with correct power domain / bandwidth pairings.
- `power-domains = <&rpmhpd RPMHPD_CX>` is correct for 6xx-gen1 GPUs.
- `#cooling-cells = <2>` is added here, enabling the thermal binding in patch 3.
- `status = "disabled"` is correct for an SoC-level dtsi — enablement comes per-board.
- GMU clocks and power domains match the RGMU binding schema.
- Address ordering (gpu, gmu, gpucc, smmu) is correct within the SoC node.

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