From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: arm64: dts: qcom: talos: Add gpu and rgmu nodes Date: Fri, 13 Mar 2026 14:34:42 +1000 Message-ID: In-Reply-To: <20260312-qcs615-spin-2-v8-2-fca38edcd6e6@oss.qualcomm.com> References: <20260312-qcs615-spin-2-v8-0-fca38edcd6e6@oss.qualcomm.com> <20260312-qcs615-spin-2-v8-2-fca38edcd6e6@oss.qualcomm.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Patch Review **Issue: GMU node unit address mismatch.** The node name is `gmu@506a000` but the `reg` property starts at `0x0506d000= `: ```dts gmu: gmu@506a000 { compatible =3D "qcom,adreno-rgmu-612.0", "qcom,adreno-rgmu"; reg =3D <0x0 0x0506d000 0x0 0x2c000>; ``` Per DT conventions, the unit address in the node name must match the first = address in the `reg` property. This should be `gmu@506d000`. For comparison= , the full GMU on SDM845 uses `gmu@506a000` with `reg =3D <0 0x0506a000 ...= >` =E2=80=94 matching correctly. The RGMU on this SoC starts at a different= offset and the node name must reflect that. This will likely trigger a `dt= bs_check` warning (`node name unit address does not match first reg entry`). Note: The binding document example (`qcom,adreno-rgmu.yaml` line 90=E2=80= =9393) itself has a mismatch (`gmu@506a000` with `reg =3D <0x05000000 0x900= 00>`) =E2=80=94 that's a pre-existing issue in the binding doc, not introdu= ced by this series, but worth fixing as a follow-up. **Rest of patch 2 looks good:** - The `pil_gpu_mem` reserved memory region at `0x97715000` with size `0x200= 0` and `no-map` is standard for GPU firmware. - The GPU node at `gpu@5000000` follows the established A6xx pattern with c= orrect `reg-names` (`kgsl_3d0_reg_memory`, `cx_mem`, `cx_dbgc`). - OPP table has 5 entries (435=E2=80=93845 MHz) with correct power domain /= bandwidth pairings. - `power-domains =3D <&rpmhpd RPMHPD_CX>` is correct for 6xx-gen1 GPUs. - `#cooling-cells =3D <2>` is added here, enabling the thermal binding in p= atch 3. - `status =3D "disabled"` is correct for an SoC-level dtsi =E2=80=94 enable= ment comes per-board. - GMU clocks and power domains match the RGMU binding schema. - Address ordering (gpu, gmu, gpucc, smmu) is correct within the SoC node. --- Generated by Claude Code Patch Reviewer