Claude review: drm/i915/display: Panel Replay BW optimization for DP2.0 tunneling

[Claude Code Review Bot <claude-review@example.com>]

Patch Review

**Reviewed-by already present from Arun R Murthy.** 

**Register bit definition looks correct:** `TRANS_DP2_PR_TUNNELING_ENABLE` at `REG_BIT(26)` — fits between existing bit 30 (`PANEL_REPLAY_ENABLE`) and bit 23 (`DEBUG_ENABLE`), so the ordering in the header is correct.

**The `intel_psr_allow_pr_bw_optimization` check is clean:** It gates on DISPLAY_VER >= 35, bw_alloc being enabled, and PR optimization being supported. The DISPLAY_VER check is appropriate since this is a new hardware feature.

**Redundant `!intel_dp_is_edp()` check in `dg2_activate_panel_replay`:**
```c
if (!intel_dp_is_edp(intel_dp) && intel_psr_allow_pr_bw_optimization(intel_dp))
    dp2_ctl_val |= TRANS_DP2_PR_TUNNELING_ENABLE;
```
The `intel_psr_allow_pr_bw_optimization()` function already calls `intel_dp_tunnel_bw_alloc_is_enabled()` and `intel_dp_tunnel_pr_optimization_supported()`, which would both return false for eDP (no tunnel). The explicit `!intel_dp_is_edp()` check is technically redundant but serves as defensive documentation — acceptable.

**Missing deactivation/disable path:** When Panel Replay is deactivated, `TRANS_DP2_PR_TUNNELING_ENABLE` (bit 26) needs to be cleared. Looking at the existing code, `intel_psr_disable_locked()` calls `intel_de_rmw()` to clear `TRANS_DP2_PANEL_REPLAY_ENABLE` on the `TRANS_DP2_CTL` register. Does it also clear bit 26? I don't see the deactivation path being updated in this patch. If the existing disable code does `intel_de_rmw(display, TRANS_DP2_CTL(...), TRANS_DP2_PANEL_REPLAY_ENABLE, 0)`, then bit 26 would be left set after disable. This is a potential bug — the tunneling enable bit should be cleared when Panel Replay is disabled. Please verify the disable path clears `TRANS_DP2_PR_TUNNELING_ENABLE` as well.

**Copy-paste in wrapper doc comment (patch 1, but affects understanding):**
```c
 * Returns %true if the BW allocation mode is supported on @intel_dp.
```
This comment in `intel_dp_tunnel_pr_optimization_supported()` says "BW allocation mode" but should say "PR BW optimization". This is a copy-paste error from `intel_dp_tunnel_bw_alloc_is_enabled`.

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