From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm: renesas: rzg2l_mipi_dsi: Increase reset deassertion delay Date: Tue, 31 Mar 2026 17:20:05 +1000 Message-ID: In-Reply-To: <20260330104450.128512-3-biju.das.jz@bp.renesas.com> References: <20260330104450.128512-1-biju.das.jz@bp.renesas.com> <20260330104450.128512-3-biju.das.jz@bp.renesas.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Patch Review **Purpose**: Replace `udelay(1)` with `fsleep(1000)` =E2=80=94 increasing f= rom 1 usec to 1 msec per the hardware manual requirement of >=3D 1 msec aft= er CMN_RSTB deassertion. **Review**: This is a straightforward and clearly correct fix. The original `udelay(1)`= was three orders of magnitude too short per the hardware manual. 1. **Use of `fsleep(1000)` is appropriate**: `fsleep()` automatically selec= ts between `udelay`, `usleep_range`, and `msleep` based on the duration. Fo= r 1000 usec, it will use `usleep_range()`, which is correct for a non-atomi= c context (this is called from the bridge enable path, which can sleep). 2. The Fixes tag and stable Cc are appropriate =E2=80=94 this was a real ha= rdware requirement being violated. **Verdict**: Clean one-liner fix. No issues. --- Generated by Claude Code Patch Reviewer