Claude review: drm/i915/display: Panel Replay BW optimization for DP2.0 tunneling

Claude Code Review Bot
2026-03-31T07:12:02Z

Patch Review

This is the main functional patch. The `intel_psr_allow_pr_bw_optimization()` helper is clean and correctly checks: not eDP, BW alloc enabled, and PR optimization supported.

**Functional concern — deactivation path does not clear `TRANS_DP2_PR_TUNNELING_ENABLE`:**

The activation in `dg2_activate_panel_replay()` sets or clears `TRANS_DP2_PR_TUNNELING_ENABLE` correctly:
```c
if (intel_psr_allow_pr_bw_optimization(intel_dp))
dp2_ctl_set |= TRANS_DP2_PR_TUNNELING_ENABLE;
else
dp2_ctl_clear = TRANS_DP2_PR_TUNNELING_ENABLE;
```

But the deactivation at `intel_psr.c:2281` only clears `TRANS_DP2_PANEL_REPLAY_ENABLE`:
```c
intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder),
TRANS_DP2_PANEL_REPLAY_ENABLE, 0);
```

This leaves `TRANS_DP2_PR_TUNNELING_ENABLE` set after Panel Replay is deactivated. This could cause the tunneling hardware to continue attempting BW optimization when PR is no longer active, which seems wrong. The deactivation should also clear `TRANS_DP2_PR_TUNNELING_ENABLE`:
```c
intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder),
TRANS_DP2_PANEL_REPLAY_ENABLE | TRANS_DP2_PR_TUNNELING_ENABLE, 0);
```

Similarly, the `intel_psr_get_config()` readback at line 4290 only checks `TRANS_DP2_PANEL_REPLAY_ENABLE` — it may be worth reading back the tunneling bit as well for debug/state verification, though this is less critical.

**The register bit definition** (`REG_BIT(26)`) and placement is consistent with the existing definitions in `intel_display_regs.h`.

**Overall**, this is a well-structured series. The deactivation path issue should be fixed before merging.