From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm: lcdif: Use dedicated set/clr registers for polarity/edge Date: Tue, 31 Mar 2026 16:48:35 +1000 Message-ID: In-Reply-To: <20260330224619.2620782-3-paulk@sys-base.io> References: <20260330224619.2620782-1-paulk@sys-base.io> <20260330224619.2620782-3-paulk@sys-base.io> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Patch Review **Improvement over the original code, but the commit message undersells it.= ** The old code: ```c writel(ctrl, lcdif->base + LCDC_V8_CTRL); ``` This was a full register write with only polarity bits set, which would **c= lobber** any other bits previously configured in `LCDC_V8_CTRL` (e.g., `CTR= L_NEG`, `CTRL_FETCH_START_OPTION_*`). Using `REG_SET`/`REG_CLR` at offsets = +4/+8 is strictly safer because it modifies only the targeted bits via atom= ic set/clear. The commit message says "It is unclear if there is a difference" =E2=80=94 = but there **is** a clear difference: the old code was a plain write that co= uld zero other CTRL bits, while `REG_SET`/`REG_CLR` are read-modify-write a= t the hardware level. The commit message should mention this as the primary= motivation rather than presenting it as cargo-culting the BSP. No functional issues with the code itself. The `else` branches correctly cl= ear the bits when the condition is false, which the old code did implicitly= (by not OR-ing them into a zero-initialized variable and then doing a full= write). --- --- Generated by Claude Code Patch Reviewer