From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: dt-bindings: arm-smmu: Update the description for Glymur GPU SMMU Date: Tue, 05 May 2026 09:19:36 +1000 Message-ID: In-Reply-To: <20260501-glymur-gpu-dt-v2-2-2f128b5596bb@oss.qualcomm.com> References: <20260501-glymur-gpu-dt-v2-0-2f128b5596bb@oss.qualcomm.com> <20260501-glymur-gpu-dt-v2-2-2f128b5596bb@oss.qualcomm.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Patch Review **Status: Minor observations.** This patch does two things: 1. Adds an `interconnects` property to the common SMMU properties: ``` + interconnects: + maxItems: 1 ``` 2. Extends the SM8750-specific compatible section to also cover Glymur: ``` - - const: qcom,sm8750-smmu-500 + - enum: + - qcom,glymur-smmu-500 + - qcom,sm8750-smmu-500 ``` **Observations:** - The `interconnects` addition at the top-level of the SMMU schema is a glo= bal change =E2=80=94 it allows `interconnects` for *all* ARM SMMU variants,= not just the Glymur one. Looking at the existing kernel tree, no current `= adreno_smmu` node (sm8550, sm8650) uses `interconnects`. This is presumably= a new requirement for Glymur. The DT binding maintainers may want to confi= rm whether this should be constrained to specific compatible strings rather= than being globally allowed. That said, `maxItems: 1` is reasonable and th= e property is well-understood in the DT ecosystem. - The sm8750 section reuse is sensible since Glymur and SM8750 share the sa= me GPU SMMU clock configuration (single "hlos" clock). --- --- Generated by Claude Code Patch Reviewer