From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: dt-bindings: display/msm: gpu: Document Adreno X2-185 Date: Sat, 16 May 2026 12:51:47 +1000 Message-ID: In-Reply-To: <20260513-glymur-gpu-dt-v4-2-f83832c3bc9a@oss.qualcomm.com> References: <20260513-glymur-gpu-dt-v4-0-f83832c3bc9a@oss.qualcomm.com> <20260513-glymur-gpu-dt-v4-2-f83832c3bc9a@oss.qualcomm.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Patch Review Adds binding constraints for `qcom,adreno-44070001`: - Restricts `reg` to exactly 2 entries (`kgsl_3d0_reg_memory`, `cx_mem`) - Adds the compatible to the A6xx+ list that defines clocks in the GMU node This correctly follows the existing pattern for A8xx chips in the binding. The 2-entry reg constraint (no separate `cx_dbgc`) aligns with the cover letter's note that cx_dbgc is now absorbed into the `kgsl_3d0_reg_memory` range. No issues. --- Generated by Claude Code Patch Reviewer