From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/bridge: tc358762: Improve SYSCTRL register defines Date: Sat, 16 May 2026 12:04:21 +1000 Message-ID: In-Reply-To: <20260513-tc358762-fixes-v3-2-6698b55008b9@ideasonboard.com> References: <20260513-tc358762-fixes-v3-0-6698b55008b9@ideasonboard.com> <20260513-tc358762-fixes-v3-2-6698b55008b9@ideasonboard.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Patch Review Adds `#include ` and defines SYSCTRL fields using `GENMAS= K_U32` and `FIELD_PREP`. Replaces the magic `0x040f` with readable field-pr= ep expressions. I verified that `FIELD_PREP(GENMASK(1,0), 3) | FIELD_PREP(G= ENMASK(3,2), 3) | FIELD_PREP(GENMASK(11,8), 4)` =3D 0x040F, matching the ol= d value exactly. One minor note: `SYSCTRL_PCLKDIV_DIV_3` is defined as `4` (not `3`). This i= s correct =E2=80=94 it's a register field value, not a divider value. But i= t could be slightly confusing without a comment. The cover letter and patch= 7's comment later explain the divider relationship (bitspp / 8 / nlanes), = which helps. No issues. **Reviewed-by worthy.** --- Generated by Claude Code Patch Reviewer