From mboxrd@z Thu Jan  1 00:00:00 1970
From: Claude Code Review Bot <claude-review@example.com>
To: dri-devel-reviews@example.com
Subject: Claude review: drm/panel: simple: add NEC NL6448BC33-70C
Date: Sat, 16 May 2026 11:43:37 +1000
Message-ID: <review-patch2-20260513-v7-1-topic-panel-simple-nl6448bc33-v1-2-9bd4b7d0eac0@pengutronix.de>
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Patch Review

This patch adds the mode definition, panel descriptor, and OF match table entry.

**Issue 1 (likely bug): Physical size uses module outline dimensions, not active area.**

The `panel_desc` struct documents `size.width` and `size.height` as "Width/Height (in mm) of the **active display area**" (panel-simple.c lines 79-86). The patch uses:

```c
.size = {
    .width = 243,
    .height = 185,
},
```

These values (243 x 185 mm) correspond to the **module outline dimensions** of the NL6448BC33-70C, not the active display area. The active area for this panel is 211.2 x 158.4 mm. Using the outline dimensions inflates the reported physical size, leading to incorrect DPI calculations (and undersized rendering on any compositor that uses this information). This should be:

```c
.size = {
    .width = 211,
    .height = 158,
},
```

**Item 2 (worth verifying): Vertical sync pulse width of 31 lines is unusual.**

```c
.vsync_start = 480 + 2,
.vsync_end = 480 + 2 + 31,
.vtotal = 480 + 2 + 31 + 31,
```

This gives VFP=2, VSW=31, VBP=31, vtotal=544. The NL6448BC33 family datasheets I'm aware of typically specify VSW=2 (not 31), VFP=10, VBP=33, for vtotal=525 and ~60 Hz refresh. With vtotal=544, the refresh rate works out to approximately 57.8 Hz (25175000 / (800 * 544)). The submitter should confirm these vertical timing values against the actual -70C variant datasheet. A 31-line sync pulse is very atypical for this class of panel.

**Item 3 (minor, worth confirming): Sync polarity.**

```c
.flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC,
```

Standard 640x480@60Hz VGA uses negative sync (NVSYNC | NHSYNC). Some NL6448BC33 variants accept either polarity, so positive may be valid for the -70C, but the submitter should confirm this matches the datasheet.

**Everything else looks correct:**
- The pixel clock of 25175 kHz matches the standard VGA dot clock.
- Horizontal timings (HFP=16, HSW=48, HBP=96, htotal=800) match standard VGA horizontal timing.
- `bpc = 6` with `bus_format = MEDIA_BUS_FMT_RGB666_1X18` is consistent (6 bits x 3 channels = 18 bits).
- `bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE` follows the same pattern as the existing `nec_nl4827hc19_05b` entry.
- The OF match table entry is correctly placed in alphabetical order.

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