From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: dt-bindings: display/msm/gpu: Document Adreno 810 GPU Date: Sat, 16 May 2026 10:05:41 +1000 Message-ID: In-Reply-To: <20260515-adreno-810-v6-2-fbe04c7203e1@pm.me> References: <20260515-adreno-810-v6-0-fbe04c7203e1@pm.me> <20260515-adreno-810-v6-2-fbe04c7203e1@pm.me> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Patch Review **Status: Looks good** Adds the `qcom,adreno-44010000` compatible string in two places: 1. Shares the register layout constraint block with `qcom,adreno-44070001` (X285) by converting from `const` to `enum`: ``` - const: qcom,adreno-44070001 + enum: + - qcom,adreno-44010000 + - qcom,adreno-44070001 ``` 2. Adds the compatible to the list of GPUs whose clocks are defined in the GMU node. Both additions are correct. The register layout sharing with X285 is consistent with the DTS in patch 7 which uses the same reg-names (`kgsl_3d0_reg_memory`, `cx_mem`). --- Generated by Claude Code Patch Reviewer