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From: Claude Code Review Bot <claude-review@example.com>
To: dri-devel-reviews@example.com
Subject: Claude review: drm/panel: simple: add NEC NL6448BC33-70C
Date: Sat, 16 May 2026 09:23:02 +1000	[thread overview]
Message-ID: <review-patch2-20260515-v7-1-topic-panel-simple-nl6448bc33-v2-2-74ab0baa1817@pengutronix.de> (raw)
In-Reply-To: <20260515-v7-1-topic-panel-simple-nl6448bc33-v2-2-74ab0baa1817@pengutronix.de>

Patch Review

**Status: One question on timing values.**

The `panel_desc` structure is well-formed and follows conventions:

```c
static const struct panel_desc nec_nl6448bc33_70c = {
	.modes = &nec_nl6448bc33_70c_mode,
	.num_modes = 1,
	.bpc = 6,
	.size = {
		.width = 211,
		.height = 158,
	},
	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
	.bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
	.connector_type = DRM_MODE_CONNECTOR_LVDS,
};
```

- `.bpc = 6` with `MEDIA_BUS_FMT_RGB666_1X18` — consistent (6 bits × 3 channels = 18 bits).
- `.connector_type = DRM_MODE_CONNECTOR_LVDS` — correctly set (the neighboring `nec_nl4827hc19_05b` omits this and would hit the "Specify missing connector_type" warning at runtime).
- `.size` = 211×158 mm — correct for a 10.4" panel with 4:3 aspect (10.4" × 4/5 ≈ 211 mm, 10.4" × 3/5 ≈ 158 mm).
- OF match table entry is in correct alphabetical position.

**Timing concern:**

```c
static const struct drm_display_mode nec_nl6448bc33_70c_mode = {
	.clock = 25175,
	.hdisplay = 640,
	.hsync_start = 640 + 16,      /* HFP = 16 */
	.hsync_end = 640 + 16 + 48,   /* HSW = 48 */
	.htotal = 640 + 16 + 48 + 96, /* HBP = 96 */
	.vdisplay = 480,
	.vsync_start = 480 + 2,       /* VFP = 2  */
	.vsync_end = 480 + 2 + 31,    /* VSW = 31 */
	.vtotal = 480 + 2 + 31 + 31,  /* VBP = 31 */
	.flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC,
};
```

The htotal (800) is standard for 640×480, but:

1. **HSW and HBP appear swapped vs. standard VGA** — standard 640×480@60 has HSW=96 and HBP=48, i.e. the reverse of what's here. If these values come from the datasheet they may be correct, but it's worth double-checking.

2. **vtotal = 544 instead of 525** — this yields a refresh rate of 25175000 / (800 × 544) ≈ **57.85 Hz**, which is below the typical 59.94 Hz. The vertical sync width of 31 lines and back porch of 31 lines are quite different from standard VGA (VSW=2, VBP=33). Again, this may be correct per the panel's specifications, but the submitter should confirm these are from the NL6448BC33-70C datasheet and not a transcription error.

Everything else — code structure, naming, placement — looks correct and ready to merge pending timing confirmation.

---
Generated by Claude Code Patch Reviewer

  reply	other threads:[~2026-05-15 23:23 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-15 11:46 [PATCH v2 0/2] Add NEC LCD Technologies NL6448BC33-70C Panel Support Steffen Trumtrar
2026-05-15 11:46 ` [PATCH v2 1/2] dt-bindings: display: simple: Add NEC NL6448BC33-70C panel Steffen Trumtrar
2026-05-15 17:09   ` Conor Dooley
2026-05-15 23:23   ` Claude review: " Claude Code Review Bot
2026-05-15 11:46 ` [PATCH v2 2/2] drm/panel: simple: add NEC NL6448BC33-70C Steffen Trumtrar
2026-05-15 23:23   ` Claude Code Review Bot [this message]
2026-05-15 23:23 ` Claude review: Add NEC LCD Technologies NL6448BC33-70C Panel Support Claude Code Review Bot
  -- strict thread matches above, loose matches on Subject: below --
2026-05-13 16:16 [PATCH 0/2] " Steffen Trumtrar
2026-05-13 16:16 ` [PATCH 2/2] drm/panel: simple: add NEC NL6448BC33-70C Steffen Trumtrar
2026-05-16  1:43   ` Claude review: " Claude Code Review Bot

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