From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: dt-bindings: display/msm: gpu: Document Adreno X2-185 Date: Mon, 25 May 2026 18:58:50 +1000 Message-ID: In-Reply-To: <20260522-glymur-gpu-dt-v5-2-562c406b210c@oss.qualcomm.com> References: <20260522-glymur-gpu-dt-v5-0-562c406b210c@oss.qualcomm.com> <20260522-glymur-gpu-dt-v5-2-562c406b210c@oss.qualcomm.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Patch Review **Summary:** Adds DT binding constraints for `qcom,adreno-44070001` =E2=80= =94 limits reg/reg-names to exactly 2 items, and adds this compatible to th= e list of GPUs that define clocks in the GMU node rather than the GPU node. The constraints are correct: - 2 reg entries (`kgsl_3d0_reg_memory` and `cx_mem`) match what patch 4 pro= vides, correctly omitting `cx_dbgc` since the cover letter notes it's withi= n the kgsl_3d0_reg_memory range on this SoC. - Adding to the "clocks: false" list is appropriate since A8xx GPUs define = clocks on the GMU node. The `reg-names` constraint only specifies `minItems`/`maxItems` without lis= ting the actual names. This is fine because the base schema (line 59-64 of = gpu.yaml) already defines the ordered items, and the min/max here simply re= stricts which subset is valid. The v5 changelog notes this was relaxed per = reviewer feedback from Krzysztof. Looks good, no issues. --- Generated by Claude Code Patch Reviewer