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From: Claude Code Review Bot <claude-review@example.com>
To: dri-devel-reviews@example.com
Subject: Claude review: drm/panfrost: Make reset sequence deal with an active HWPerf session
Date: Wed, 27 May 2026 15:22:49 +1000	[thread overview]
Message-ID: <review-patch2-20260526-claude-fixes-v1-2-16e92eaa4949@collabora.com> (raw)
In-Reply-To: <20260526-claude-fixes-v1-2-16e92eaa4949@collabora.com>

Patch Review

**Status: Reasonable approach with one ordering concern.**

The design is sound: during a GPU reset, if perfcnt is active, do the `panfrost_mmu_as_put()` before `panfrost_mmu_reset()` zeroes the refcounts, and set a flag so the later disable path skips the (now-redundant) put. This prevents the WARN at `panfrost_mmu.c:336`:
```c
atomic_dec(&mmu->as_count);
WARN_ON(atomic_read(&mmu->as_count) < 0);
```

**Refactoring of GPU register writes** into `panfrost_perfcnt_gpu_disable()` is clean and eliminates duplication across init, fini, disable, and the new reset path. One note: the original `panfrost_perfcnt_disable_locked` wrote the enable registers first and the CFG mode-off last, while `panfrost_perfcnt_gpu_disable` writes CFG mode-off first:
```c
+static void panfrost_perfcnt_gpu_disable(struct panfrost_device *pfdev)
+{
+	gpu_write(pfdev, GPU_PERFCNT_CFG,
+		  GPU_PERFCNT_CFG_MODE(GPU_PERFCNT_CFG_MODE_OFF));
+	gpu_write(pfdev, GPU_PRFCNT_JM_EN, 0x0);
```
This order reversal is fine for disable (clearing config then enables is no worse than the reverse), but it's worth noting intentionally.

**Ordering concern**: `panfrost_perfcnt_reset()` is called after `panfrost_gpu_soft_reset()` but *before* `panfrost_gpu_power_on()`:
```c
panfrost_gpu_soft_reset(pfdev);
panfrost_perfcnt_reset(pfdev);   // <-- here
panfrost_gpu_power_on(pfdev);
```
Inside `panfrost_perfcnt_reset()`, `panfrost_perfcnt_gpu_disable()` writes to GPU registers and `panfrost_mmu_as_put()` may write to MMU registers -- all on a soft-reset GPU that hasn't been powered back on. The register writes are likely harmless (they'll be overwritten by the subsequent `panfrost_mmu_reset`), but it would be cleaner to skip the `panfrost_perfcnt_gpu_disable()` call here since the GPU was just soft-reset and the registers are already in their default state. Only the `panfrost_mmu_as_put()` and the flag-set are needed in the reset path.

**EAGAIN semantics**: Returning `-EAGAIN` from `panfrost_ioctl_perfcnt_dump` is a reasonable choice, signaling the user to retry after a disable/enable cycle. The comment explains this well.

---

---
Generated by Claude Code Patch Reviewer

  reply	other threads:[~2026-05-27  5:22 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-25 23:03 [PATCH 0/4] RPM, percnt and other minor fixes for Panfrost Adrián Larumbe
2026-05-25 23:03 ` [PATCH 1/4] drm/panfrost: Check another bo field for cache option query Adrián Larumbe
2026-05-27  5:22   ` Claude review: " Claude Code Review Bot
2026-05-25 23:03 ` [PATCH 2/4] drm/panfrost: Make reset sequence deal with an active HWPerf session Adrián Larumbe
2026-05-27  5:22   ` Claude Code Review Bot [this message]
2026-05-25 23:03 ` [PATCH 3/4] drm/panfrost: Prevent division by 0 Adrián Larumbe
2026-05-27  5:22   ` Claude review: " Claude Code Review Bot
2026-05-25 23:03 ` [PATCH 4/4] drm/panfrost: Fix RPM so device suspends when no jobs are in flight Adrián Larumbe
2026-05-27  5:22   ` Claude review: " Claude Code Review Bot
2026-05-27  5:22 ` Claude review: RPM, percnt and other minor fixes for Panfrost Claude Code Review Bot

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