From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/amdgpu/mes12: fix queue init wptr reset Date: Thu, 04 Jun 2026 13:17:09 +1000 Message-ID: In-Reply-To: <20260602050354.2237095-3-runyu.xiao@seu.edu.cn> References: <20260602050354.2237095-1-runyu.xiao@seu.edu.cn> <20260602050354.2237095-3-runyu.xiao@seu.edu.cn> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Patch Review **The change:** ```c - *(ring->wptr_cpu_addr) =3D 0; + atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); ``` At `mes_v12_0.c:1479`, in the reset/suspend path of `mes_v12_0_queue_init()= `. **Correctness:** Same analysis as patch 1. The writer `mes_v12_0_ring_set_w= ptr()` (line 58) uses `atomic64_set()` and the reader `mes_v12_0_ring_get_w= ptr()` (line 76) uses `atomic64_read()`. The fix aligns the reset path with= these. **Fixes tag:** `Fixes: 785f0f9fe742 ("drm/amdgpu: Add mes v12_0 ip block su= pport (v4)")` =E2=80=94 reasonable, identifies when the v12 queue_init was = introduced. **Same observation about rptr:** `mes_v12_0_ring_get_rptr()` (line 67) uses= `return *ring->rptr_cpu_addr` =E2=80=94 32-bit read =E2=80=94 so leaving t= he rptr reset as a 32-bit store is consistent. **No issues with this patch.** --- **Summary:** Both patches are correct, minimal, and well-scoped. The commit= messages are clear and honest about testing limitations (build-tested only= , no hardware). The series makes the reset path consistent with the normal = read/write accessors. The only thing worth noting to the author is that the= cover letter claims this was audited on "Linux v6.18.21" which doesn't exi= st =E2=80=94 v6.18 hasn't had 21 point releases. This is likely a version n= umbering mistake and doesn't affect the patches themselves. --- Generated by Claude Code Patch Reviewer