Claude review: clk: renesas: r9a09g047: Add support for DSI clocks and resets

Claude Code Review Bot
2026-04-12T02:45:57Z

Patch Review

**Observation**: `dsi_0_vclk1` uses `CLK_SMUX2_DSI0_CLK` and `dsi_0_vclk2` uses `CLK_SMUX2_DSI1_CLK`. This means vclk1 is sourced from PLLDSI0's mux and vclk2 from PLLDSI1's mux, which aligns with the cover letter description.

**Minor note**: The `dsi_0_vclk2` entry is placed after `tsu_1_pclk` at a distant location (module index 25,0 vs 14,x for the other DSI clocks). This matches the hardware register layout but could use a comment explaining why it's separate from the other DSI module clocks. However this may just be the natural ordering.

No issues.

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Generated by Claude Code Patch Reviewer