[PATCH v6 19/21] arm64: dts: renesas: r9a09g047: Add vspd{0,1} nodes

Tommaso Merciai
2026-04-08T10:40:27Z

Add vspd{0,1} nodes to RZ/G3E SoC DTSI.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
v5->v6:
- No changes.

v4->v5:
- No changes.

v3->v4:
- No changes.

v2->v3:
- No changes.

v1->v2:
- Squashed vspd0 and vspd1 patches into a single patch.
- Collected tags.

arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 28 ++++++++++++++++++++++
1 file changed, 28 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
index 3115ab4b050f..f2fdaadd9d39 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -1608,6 +1608,34 @@ fcpvd1: fcp@164a0000 {
resets = <&cpg 0x11e>;
power-domains = <&cpg>;
};
+
+ vspd0: vsp@16480000 {
+ compatible = "renesas,r9a09g047-vsp2",
+ "renesas,r9a07g044-vsp2";
+ reg = <0 0x16480000 0 0x10000>;
+ interrupts = <GIC_SPI 881 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 0xed>,
+ <&cpg CPG_MOD 0xee>,
+ <&cpg CPG_MOD 0xef>;
+ clock-names = "aclk", "pclk", "vclk";
+ resets = <&cpg 0xdc>;
+ power-domains = <&cpg>;
+ renesas,fcp = <&fcpvd0>;
+ };
+
+ vspd1: vsp@164b0000 {
+ compatible = "renesas,r9a09g047-vsp2",
+ "renesas,r9a07g044-vsp2";
+ reg = <0 0x164b0000 0 0x10000>;
+ interrupts = <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 0x1a8>,
+ <&cpg CPG_MOD 0x1a9>,
+ <&cpg CPG_MOD 0x1aa>;
+ clock-names = "aclk", "pclk", "vclk";
+ resets = <&cpg 0x11e>;
+ power-domains = <&cpg>;
+ renesas,fcp = <&fcpvd1>;
+ };
};

stmmac_axi_setup: stmmac-axi-config {
--
2.43.0