Claude review: clk: renesas: r9a09g047: Add CLK_PLLDSI{0,1} clocks

Claude Code Review Bot
2026-04-12T02:45:56Z

Patch Review

Adds PLLDSI0 and PLLDSI1 PLL definitions and their frequency limits in `include/linux/clk/renesas.h`.

**Observation**: The DSI0 and DSI1 limits differ only in `fout.max` (1218 MHz vs 609 MHz). All other parameters are identical. This could be a single macro parameterized by `fout_max`, but the current approach with two separate macros is clear and matches existing patterns in the file.

No issues. Has Reviewed-by from Geert.

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