From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/i915/dp: Always enable AS SDP if supported by source + sink Date: Sun, 12 Apr 2026 12:51:30 +1000 Message-ID: In-Reply-To: <20260408084239.1295325-27-ankit.k.nautiyal@intel.com> References: <20260408084239.1295325-1-ankit.k.nautiyal@intel.com> <20260408084239.1295325-27-ankit.k.nautiyal@intel.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Patch Review Changes `intel_dp_needs_as_sdp()` to enable AS SDP when: 1. Aux-less ALPM is active and async video timing is NOT supported (sink requires AS SDP during PR active), OR 2. VRR is *possible* (`intel_vrr_possible()` rather than `vrr.enable`) The change from `vrr.enable` to `intel_vrr_possible()` is significant. `intel_vrr_possible()` checks `crtc_state->vrr.flipline` (which is set when the mode is within VRR range), meaning AS SDP is enabled even when VRR is not currently active but the display could support it. The commit message justifies this: turning on VRR later would otherwise require a full modeset to increase the guardband. However, this means AS SDP bandwidth is always reserved for VRR-capable panels even if VRR is never used. The tradeoff is acceptable for correctness. Missing R-b. --- Generated by Claude Code Patch Reviewer