From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: soc: qcom: ubwc: sort out the rest of the UBWC swizzle settings Date: Mon, 25 May 2026 21:42:02 +1000 Message-ID: In-Reply-To: <20260520-ubwc-rework-v5-27-72f2749bc807@oss.qualcomm.com> References: <20260520-ubwc-rework-v5-0-72f2749bc807@oss.qualcomm.com> <20260520-ubwc-rework-v5-27-72f2749bc807@oss.qualcomm.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Patch Review Replaces `ubwc_swizzle` field entirely with `flags`: ```c - u32 ubwc_swizzle; + unsigned int flags; +#define UBWC_FLAG_DISABLE_SWIZZLE_LVL2 BIT(0) +#define UBWC_FLAG_DISABLE_SWIZZLE_LVL3 BIT(1) ``` The `qcom_ubwc_swizzle()` helper now defaults to LVL2|LVL3 enabled and only clears bits if the corresponding `UBWC_FLAG_DISABLE_*` is set. Only two SoCs need flags: `sa8775p` (disables LVL2) and `glymur` (disables both). This is a much cleaner representation. The default-enabled-with-opt-out pattern reduces the number of SoCs that need to specify anything. --- Generated by Claude Code Patch Reviewer