From: Claude Code Review Bot <claude-review@example.com>
To: dri-devel-reviews@example.com
Subject: Claude review: drm/xe/xe_hw_error: Integrate DRM RAS with hardware error handling
Date: Tue, 03 Mar 2026 14:32:50 +1000 [thread overview]
Message-ID: <review-patch3-20260228080858.3063532-10-riana.tauro@intel.com> (raw)
In-Reply-To: <20260228080858.3063532-10-riana.tauro@intel.com>
Patch Review
**Loss of FATAL vs NONFATAL distinction in log messages:**
The old code logged distinct strings ("CORRECTABLE", "NONFATAL", "FATAL"). The new code collapses NONFATAL and FATAL into "uncorrectable-errors":
```c
+static enum drm_xe_ras_error_severity hw_err_to_severity(const enum hardware_error hw_err)
+{
+ if (hw_err == HARDWARE_ERROR_CORRECTABLE)
+ return DRM_XE_RAS_ERR_SEV_CORRECTABLE;
+
+ /* Uncorrectable errors comprise of both fatal and non-fatal errors */
+ return DRM_XE_RAS_ERR_SEV_UNCORRECTABLE;
+}
```
While this mapping is correct for the RAS counter abstraction, using the severity string directly in kernel log messages (e.g. `"HEC FW %s %s reported"`) loses important diagnostic information. A FATAL error requiring firmware flash vs a NONFATAL error should be distinguishable in `dmesg`. Consider keeping a separate `hw_error_to_str()` for log messages while using `hw_err_to_severity()` for counter bucketing.
**`hw_error_info_init` only for PVC but handler is still Battlemage-gated:**
```c
+static int hw_error_info_init(struct xe_device *xe)
+{
+ if (xe->info.platform != XE_PVC)
+ return 0;
+ return xe_drm_ras_init(xe);
+}
```
In this patch, `hw_error_source_handler` still checks `xe->info.platform != XE_BATTLEMAGE`, so Battlemage will still enter the handler but without RAS info initialized. The `info` pointer will be NULL. This is addressed in patch 4 with the `if (!info) goto clear_reg` guard, but it means this patch alone has a potential NULL dereference on Battlemage if applied independently (broken bisectability).
---
---
Generated by Claude Code Patch Reviewer
next prev parent reply other threads:[~2026-03-03 4:32 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-28 8:08 [PATCH v9 0/5] Introduce DRM_RAS using generic netlink for RAS Riana Tauro
2026-02-28 8:08 ` [PATCH v9 1/5] drm/ras: Introduce the DRM RAS infrastructure over generic netlink Riana Tauro
2026-02-28 16:04 ` Jakub Kicinski
2026-03-03 4:32 ` Claude review: " Claude Code Review Bot
2026-02-28 8:08 ` [PATCH v9 2/5] drm/xe/xe_drm_ras: Add support for XE DRM RAS Riana Tauro
2026-03-03 4:32 ` Claude review: " Claude Code Review Bot
2026-02-28 8:08 ` [PATCH v9 3/5] drm/xe/xe_hw_error: Integrate DRM RAS with hardware error handling Riana Tauro
2026-03-03 4:32 ` Claude Code Review Bot [this message]
2026-02-28 8:08 ` [PATCH v9 4/5] drm/xe/xe_hw_error: Add support for Core-Compute errors Riana Tauro
2026-03-03 4:32 ` Claude review: " Claude Code Review Bot
2026-02-28 8:08 ` [PATCH v9 5/5] drm/xe/xe_hw_error: Add support for PVC SoC errors Riana Tauro
2026-03-03 4:32 ` Claude review: " Claude Code Review Bot
2026-03-03 4:32 ` Claude review: Introduce DRM_RAS using generic netlink for RAS Claude Code Review Bot
-- strict thread matches above, loose matches on Subject: below --
2026-03-04 7:44 [PATCH v10 0/5] " Riana Tauro
2026-03-04 7:44 ` [PATCH v10 3/5] drm/xe/xe_hw_error: Integrate DRM RAS with hardware error handling Riana Tauro
2026-03-05 3:47 ` Claude review: " Claude Code Review Bot
2026-02-23 6:05 [PATCH v8 0/5] Introduce DRM_RAS using generic netlink for RAS Riana Tauro
2026-02-23 6:05 ` [PATCH v8 3/5] drm/xe/xe_hw_error: Integrate DRM RAS with hardware error handling Riana Tauro
2026-02-24 0:45 ` Claude review: " Claude Code Review Bot
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