From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/bridge: fsl-ldb: Add support for i.MX94 Date: Thu, 05 Mar 2026 13:34:48 +1000 Message-ID: In-Reply-To: <20260304-dcif-upstreaming-v8-3-bec5c047edd4@oss.nxp.com> References: <20260304-dcif-upstreaming-v8-0-bec5c047edd4@oss.nxp.com> <20260304-dcif-upstreaming-v8-3-bec5c047edd4@oss.nxp.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Patch Review Adds `max_clk_khz` to the devdata struct and uses it in `fsl_ldb_mode_valid= ()` instead of the previously hardcoded 80000 kHz. The i.MX94 supports 165 = MHz. The change from: ```c if (mode->clock > (fsl_ldb_is_dual(fsl_ldb) ? 160000 : 80000)) ``` to: ```c if (mode->clock > (fsl_ldb_is_dual(fsl_ldb) ? 2 : 1) * fsl_ldb->devdata->ma= x_clk_khz) ``` is correct and clean. Note the i.MX94 register offsets (`ldb_ctrl =3D 0x04`= , `lvds_ctrl =3D 0x08`) are different from the other variants =E2=80=94 thi= s is because it's nested inside the LVDS CSR syscon as a child node, so off= sets are relative to the child's reg. No issues. --- Generated by Claude Code Patch Reviewer