From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/msm/dpu: support plane splitting in quad-pipe case Date: Fri, 13 Mar 2026 14:21:22 +1000 Message-ID: In-Reply-To: <20260312-msm-next-quad-pipe-split-v19-3-4ffa2b06c996@linaro.org> References: <20260312-msm-next-quad-pipe-split-v19-0-4ffa2b06c996@linaro.org> <20260312-msm-next-quad-pipe-split-v19-3-4ffa2b06c996@linaro.org> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Patch Review **Review: Core logic change, mostly correct but with some concerns.** This extends `dpu_plane_split()` to iterate over multiple mixer stages. Key logic: - `num_stages = (num_lm + 1) / 2` for virtual planes (1 stage for 1-2 LMs, 2 stages for 3-4 LMs) - Each stage covers a horizontal band of the display - For each stage, the plane's dst_rect is clipped against the mixer rectangle - Within each stage, a wide-plane split may further divide into 2 pipes Concerns: 1. **`dpu_crtc_get_num_lm()` is called before topology is finalized in some paths.** The function reads `cstate->num_mixers`. In patch 2, `dpu_plane_split()` is called from `dpu_plane_assign_resources()` / `dpu_plane_virtual_assign_resources()`, which happens during CRTC check after `dpu_crtc_assign_resources()` has run. So `num_mixers` should be set by then. But this ordering dependency is subtle and fragile. 2. **`dpu_plane_atomic_check_sspp()` now loops over all `PIPES_PER_PLANE` (4) entries.** This is correct but changes from checking exactly pipe[0] and pipe[1] to checking any non-zero-width pipe_cfg. For the non-virtual case with `num_stages=1`, only pipe_cfg[0] and pipe_cfg[1] are populated, and pipe_cfg[2]/pipe_cfg[3] should be zero-initialized from `dpu_plane_state` allocation. This should be safe. 3. **The `memset(pipe_cfg, 0, 2 * sizeof(struct dpu_sw_pipe_cfg))` at line 943** clears both pipe_cfg and r_pipe_cfg when the plane doesn't intersect a mixer rect. This relies on `pipe_cfg` and `r_pipe_cfg` being contiguous in the array, which they are (`pipe_cfg[cfg_idx]` and `pipe_cfg[cfg_idx + 1]`). Correct but uses a fragile assumption about memory layout. 4. **The mixer_rect calculation** `stage_id * mode->hdisplay / num_stages` uses integer division. For odd hdisplay values with num_stages=2, the split might not be perfectly symmetric (e.g., 1081/2 = 540 vs 541). This should match the hardware configuration but is worth verifying. Has Reviewed-by from Dmitry Baryshkov and Jessica Zhang. **Minor concerns noted above.** --- Generated by Claude Code Patch Reviewer