From: Claude Code Review Bot <claude-review@example.com>
To: dri-devel-reviews@example.com
Subject: Claude review: drm/i915/display: Disable Panel Replay for DP-tunneling without optimization
Date: Fri, 13 Mar 2026 14:30:27 +1000 [thread overview]
Message-ID: <review-patch3-20260312050035.3493690-4-animesh.manna@intel.com> (raw)
In-Reply-To: <20260312050035.3493690-4-animesh.manna@intel.com>
Patch Review
**Typo in debug message:**
```c
"Panel Replay is disabled as DP tunelling enabled without optimization\n"
```
"tunelling" → "tunneling" (missing 'n').
**Placement of the check:** The check is inserted after computing `link_off_after_as_sdp_when_pr_active` and `disable_as_sdp_when_pr_active` but before the `!intel_dp_is_edp()` early return. This means these `crtc_state` fields get set even when Panel Replay will be disabled by this new check. Those fields are only meaningful when Panel Replay is active, so this is a minor inefficiency but not a bug — the state is ignored when `has_panel_replay` ends up false.
**The spec quote is helpful** — it clearly justifies why Panel Replay must be disabled when the bridge doesn't support PR tunneling optimization. Good commit message.
**Ordering concern between patch 2 and patch 3:** Patch 2 enables the optimization bit in the activation path, and patch 3 disables Panel Replay entirely when the optimization isn't supported. If patch 2 were applied alone (without patch 3), Panel Replay would still be enabled on tunneled connections without optimization support — just without the optimization bit set. The DP spec says PR should not be enabled in that case. Consider whether these should be reordered or squashed so there's no window where the driver violates the spec, even bisecting between patches.
**Summary of issues to address:**
1. **Typo** in patch 1 doc: "optimiation" → "optimization"
2. **Typo** in patch 3 debug message: "tunelling" → "tunneling"
3. **Copy-paste error** in patch 1 `intel_dp_tunnel_pr_optimization_supported()` doc: says "BW allocation mode" instead of "PR BW optimization"
4. **Missing deactivation path** in patch 2: verify that `TRANS_DP2_PR_TUNNELING_ENABLE` is cleared when Panel Replay is disabled
5. **Patch ordering**: patch 3 should logically come before patch 2 to avoid a bisect-unsafe spec violation window
6. **Minor**: consider adding `pr_optimization_support` change detection in `update_tunnel_regs()` for consistency with `bw_alloc_supported`
---
Generated by Claude Code Patch Reviewer
next prev parent reply other threads:[~2026-03-13 4:30 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-12 5:00 [PATCH v7 0/3] Panel Replay BW optimization Animesh Manna
2026-03-12 5:00 ` [PATCH v7 1/3] drm/i915/display: Add drm helper to check pr optimization support Animesh Manna
2026-03-12 6:40 ` Hogander, Jouni
2026-03-12 8:36 ` Manna, Animesh
2026-03-13 4:30 ` Claude review: " Claude Code Review Bot
2026-03-12 5:00 ` [PATCH v7 2/3] drm/i915/display: Panel Replay BW optimization for DP2.0 tunneling Animesh Manna
2026-03-12 6:44 ` Hogander, Jouni
2026-03-12 8:44 ` Manna, Animesh
2026-03-13 4:30 ` Claude review: " Claude Code Review Bot
2026-03-12 5:00 ` [PATCH v7 3/3] drm/i915/display: Disable Panel Replay for DP-tunneling without optimization Animesh Manna
2026-03-12 6:17 ` Hogander, Jouni
2026-03-12 8:33 ` Manna, Animesh
2026-03-13 4:30 ` Claude Code Review Bot [this message]
2026-03-12 8:05 ` [PATCH v7 0/3] Panel Replay BW optimization Hogander, Jouni
2026-03-12 8:41 ` Manna, Animesh
2026-03-12 15:18 ` Imre Deak
2026-03-13 4:30 ` Claude review: " Claude Code Review Bot
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