Claude review: drm: renesas: rzg2l_mipi_dsi: Fix deassert of CMN_RSTB signal

[Claude Code Review Bot <claude-review@example.com>]

Patch Review

Moves `reset_control_deassert()` from `rzg2l_mipi_dsi_dphy_init()` to `rzg2l_mipi_dsi_startup()`, placing it after Link register writes. This ensures PHY timing registers and Link registers are written before deasserting CMN_RSTB, per Section 34.4.2.1.

```c
+	if (dsi->rstc) {
+		ret = reset_control_deassert(dsi->rstc);
+		if (ret < 0)
+			goto err_phy;
+
+		udelay(1);
+	}
```

**The NULL check is unnecessary but harmless.** `reset_control_deassert(NULL)` returns 0, so the `if (dsi->rstc)` guard is not needed for correctness. However, it does skip the `udelay(1)` on RZ/V2H where there's no reset to deassert, which is a minor optimization. This is fine.

**Note:** The `udelay(1)` kept here is the old value; patch 4 will change it to `fsleep(1000)`. This is fine for bisectability — the ordering fix is separated from the timing fix.

**No Fixes tag or stable Cc:** Unlike patches 1 and 2, this patch lacks `Fixes:` and `Cc: stable` tags, even though it arguably has a stronger case for them than patch 2 — it's fixing the order of operations per the hardware manual. This seems inconsistent with the rest of the series.

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