From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm: renesas: rzg2l_mipi_dsi: Fix deassert of CMN_RSTB signal Date: Sun, 22 Mar 2026 04:12:40 +1000 Message-ID: In-Reply-To: <20260319164833.409126-4-biju.das.jz@bp.renesas.com> References: <20260319164833.409126-1-biju.das.jz@bp.renesas.com> <20260319164833.409126-4-biju.das.jz@bp.renesas.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Patch Review Moves `reset_control_deassert()` from `rzg2l_mipi_dsi_dphy_init()` to `rzg2= l_mipi_dsi_startup()`, placing it after Link register writes. This ensures = PHY timing registers and Link registers are written before deasserting CMN_= RSTB, per Section 34.4.2.1. ```c + if (dsi->rstc) { + ret =3D reset_control_deassert(dsi->rstc); + if (ret < 0) + goto err_phy; + + udelay(1); + } ``` **The NULL check is unnecessary but harmless.** `reset_control_deassert(NUL= L)` returns 0, so the `if (dsi->rstc)` guard is not needed for correctness.= However, it does skip the `udelay(1)` on RZ/V2H where there's no reset to = deassert, which is a minor optimization. This is fine. **Note:** The `udelay(1)` kept here is the old value; patch 4 will change i= t to `fsleep(1000)`. This is fine for bisectability =E2=80=94 the ordering = fix is separated from the timing fix. **No Fixes tag or stable Cc:** Unlike patches 1 and 2, this patch lacks `Fi= xes:` and `Cc: stable` tags, even though it arguably has a stronger case fo= r them than patch 2 =E2=80=94 it's fixing the order of operations per the h= ardware manual. This seems inconsistent with the rest of the series. --- Generated by Claude Code Patch Reviewer