Claude review: drm/panfrost: Add bus_ace optional clock support for RZ/G2L

[Claude Code Review Bot <claude-review@example.com>]

Patch Review

This adds an optional `bus_ace` clock alongside the existing `bus` clock. The init/fini paths look correct. However, there is an issue in the runtime resume error handling and a question about the runtime resume enable path.

**Issue: bus_ace_clock enable is gated by GPU_PM_RT but only conditionally needed**

In `panfrost_device_runtime_resume()`, the new `clk_enable(pfdev->bus_ace_clock)` call is placed *inside* the `if (pfdev->comp->pm_features & BIT(GPU_PM_RT))` block:

```c
	if (pfdev->comp->pm_features & BIT(GPU_PM_RT)) {
		...
		ret = clk_enable(pfdev->bus_clock);
		if (ret)
			goto err_bus_clk;

		ret = clk_enable(pfdev->bus_ace_clock);
		if (ret)
			goto err_bus_ace_clk;
	}
```

This is fine because `clk_enable(NULL)` returns 0, and the clock is optional, so it will be NULL on platforms that don't need it. However, the commit message says the clock is needed for RZ/G2L, yet looking at the existing tree, RZ/G2L (`r9a07g044`) uses `default_pm_rt_data` — so the `GPU_PM_RT` gate is the correct place. This seems consistent.

**Issue: `panfrost_device_resume`/`panfrost_device_suspend` (`GPU_PM_CLK_DIS` path) not updated**

The `bus_ace_clock` is not handled in `panfrost_device_resume()` and `panfrost_device_suspend()` which manage clocks for the `GPU_PM_CLK_DIS` feature. If any future SoC with `bus_ace_clock` also uses `GPU_PM_CLK_DIS`, the clock would not be properly managed during system suspend/resume. For current hardware this is not a problem since RZ/G2L only uses `GPU_PM_RT`, but it could be worth a note or a follow-up.

**The runtime resume/suspend paths look correct** for the current use case. The error cleanup properly disables `bus_clock` before falling through to `err_bus_clk`.

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