From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: gpu: nova-core: convert PFB registers to kernel register macro Date: Wed, 25 Mar 2026 07:57:34 +1000 Message-ID: In-Reply-To: <20260323-b4-nova-register-v3-3-ae2486ecef1b@nvidia.com> References: <20260323-b4-nova-register-v3-0-ae2486ecef1b@nvidia.com> <20260323-b4-nova-register-v3-3-ae2486ecef1b@nvidia.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Patch Review Notable changes: - `NV_PGSP_QUEUE_HEAD` is correctly moved from the PFB section to its own P= GSP section. - The `write_sysmem_flush_page_ga100` function now uses `Bounded:::= :from(addr).shr::().cast()` for the high add= ress bits, while still using raw `as u32` cast for the low bits. This asymm= etry is noted in the comment and seems intentional =E2=80=94 the high bits = can be proven to fit, while the low bits deliberately strip upper bits. - `NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE` fields are reordered to descending or= der per the new convention. - The `with_address(0u32)` call on line 1156 needs the `u32` type annotatio= n to disambiguate =E2=80=94 slightly awkward but correct. --- Generated by Claude Code Patch Reviewer