From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: arm64: dts: qcom: glymur: Add GPU smmu node Date: Tue, 05 May 2026 09:19:36 +1000 Message-ID: In-Reply-To: <20260501-glymur-gpu-dt-v2-3-2f128b5596bb@oss.qualcomm.com> References: <20260501-glymur-gpu-dt-v2-0-2f128b5596bb@oss.qualcomm.com> <20260501-glymur-gpu-dt-v2-3-2f128b5596bb@oss.qualcomm.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Patch Review **Status: Looks good. Already reviewed by Konrad and Dmitry.** This adds the `adreno_smmu` IOMMU node at `0x03da0000`: ``` + adreno_smmu: iommu@3da0000 { + compatible =3D "qcom,glymur-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg =3D <0x0 0x03da0000 0x0 0x40000>; ``` **Observations:** - The compatible string chain is correct: SoC-specific, then adreno-specifi= c, then generic SMMU-500 variants. - **26 interrupts** with `#global-interrupts =3D <1>`, meaning 1 global + 2= 5 context bank interrupts. This is one more context bank interrupt than sm8= 550/sm8650 (which have 24 context bank interrupts). This seems plausible fo= r a newer/larger GPU but worth confirming. - The `interconnects` property referencing `hsc_noc MASTER_GPU_TCU` is new = compared to older SoCs =E2=80=94 consistent with the binding change in patc= h 2. - Single clock (`GPU_CC_GPU_SMMU_VOTE_CLK` / "hlos") matches the sm8750 bin= ding pattern, which is simpler than sm8550's 4-clock setup. This reflects a= newer SMMU integration. - Address space is clean: SMMU at `0x03da0000` starts exactly where `cx_mem= ` ends (`0x03d9e000 + 0x2000 =3D 0x03da0000`). No issues found. --- --- Generated by Claude Code Patch Reviewer