From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: media: iris: don't specify highest_bank_bit in the source code Date: Thu, 07 May 2026 12:40:17 +1000 Message-ID: In-Reply-To: <20260507-iris-ubwc-v5-3-e9a3aee53c49@oss.qualcomm.com> References: <20260507-iris-ubwc-v5-0-e9a3aee53c49@oss.qualcomm.com> <20260507-iris-ubwc-v5-3-e9a3aee53c49@oss.qualcomm.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Patch Review Replaces `core->iris_platform_data->ubwc_config->highest_bank_bit` with direct access to the UBWC config: ```c payload = ubwc->highest_bank_bit; ``` The old field was `u32`, the new struct field is `int`. Since `highest_bank_bit` values are always positive (representing a DDR bank bit position, e.g. 16 for SM8550), the implicit conversion to `u32 payload` is safe. The key benefit: the central registry can derive HBB from runtime DDR type detection rather than using a fixed value, which was called out in the cover letter as one of the motivations for this series. No issues. --- Generated by Claude Code Patch Reviewer