From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: arm64: dts: qcom: kaanapali: add the GPU SMMU node Date: Sat, 16 May 2026 14:35:13 +1000 Message-ID: In-Reply-To: <20260512-kaana-gpu-dt-v1-3-13e1c07c2050@oss.qualcomm.com> References: <20260512-kaana-gpu-dt-v1-0-13e1c07c2050@oss.qualcomm.com> <20260512-kaana-gpu-dt-v1-3-13e1c07c2050@oss.qualcomm.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Patch Review **Status: Looks good** Adds the Adreno GPU SMMU node at `0x3da0000`. The node is placed after `gpucc@3d90000`, which is correct address ordering. The node has `#global-interrupts = <1>` with the first interrupt (GIC_SPI 674) as the global fault interrupt, followed by 25 context bank interrupts. This is a reasonable count for a modern GPU SMMU. The compatible string chain `"qcom,kaanapali-smmu-500", "qcom,adreno-smmu", "qcom,smmu-500", "arm,mmu-500"` follows the established pattern. The single "hlos" clock matches the binding added in patch 1. Properties (`dma-coherent`, `power-domains` referencing `GPU_CC_CX_GDSC`) are consistent with other recent Qualcomm GPU SMMU nodes. --- --- Generated by Claude Code Patch Reviewer