From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/msm/adreno: Sync registers from mesa Date: Mon, 25 May 2026 21:26:27 +1000 Message-ID: In-Reply-To: <20260520162454.18391-4-robin.clark@oss.qualcomm.com> References: <20260520162454.18391-1-robin.clark@oss.qualcomm.com> <20260520162454.18391-4-robin.clark@oss.qualcomm.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Patch Review Large mechanical sync of XML register definitions. The a5xx changes convert= ing split `_LO`/`_HI` reg pairs to `reg64` and the `gpu_write64()`/`gpu_rea= d64()` conversions in `a5xx_gpu.c` look correct. The new `a8xx_perfcntrs.xm= l` provides the countable enums needed by the perfcntr tables. No code logi= c concerns =E2=80=94 this is generated/synced data. --- Generated by Claude Code Patch Reviewer