From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/msm/adreno: Sync registers from mesa Date: Wed, 27 May 2026 14:42:30 +1000 Message-ID: In-Reply-To: <20260526145137.160554-4-robin.clark@oss.qualcomm.com> References: <20260526145137.160554-1-robin.clark@oss.qualcomm.com> <20260526145137.160554-4-robin.clark@oss.qualcomm.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Patch Review Bulk register XML sync. The a5xx code change to use `gpu_write64()`/`gpu_read64()` instead of separate LO/HI writes is a natural consequence of the register consolidation. The new `a8xx_perfcntrs.xml` (1929 lines) defines the a8xx performance counter register layout. This is generated/synced content, so correctness is determined by the mesa source. --- Generated by Claude Code Patch Reviewer