From mboxrd@z Thu Jan  1 00:00:00 1970
From: Claude Code Review Bot <claude-review@example.com>
To: dri-devel-reviews@example.com
Subject: Claude review: arm64: dts: rockchip: rk356x: Add NPU and its IOMMU
Date: Thu, 04 Jun 2026 16:18:12 +1000
Message-ID: <review-patch3-20260529155824.3099831-4-midgy971@gmail.com>
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Patch Review

**1. Node placement violates address ordering**

The NPU nodes are inserted between `qos_rga_wr` (0xfe158300) and `qos_npu` =
(0xfe180000):

```diff
 	qos_rga_wr: qos@fe158300 {
 		reg =3D <0x0 0xfe158300 0x0 0x20>;
 	};

+	rknn_core_0: npu@fde40000 {
```

But the NPU base address is `0xfde40000`, which is *lower* than `0xfe158300=
`. Rockchip DTS files sort nodes by unit address. These nodes should be pla=
ced earlier in the file, near other `0xfdeXXXXX` nodes.

**2. Shared interrupt between NPU and IOMMU**

```dts
rknn_core_0: npu@fde40000 {
	interrupts =3D <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
	...
};

rknn_mmu_0: iommu@fde4b000 {
	interrupts =3D <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
	...
};
```

Both the NPU core and its IOMMU use GIC_SPI 151. Verify this is correct per=
 the TRM =E2=80=94 on RK3588 the NPU cores and IOMMUs have distinct interru=
pts. Sharing an interrupt line between a device and its IOMMU can work if t=
he driver handles it, but it's unusual and worth double-checking against th=
e hardware documentation.

**3. `assigned-clock-rates` value**

```dts
assigned-clocks =3D <&scmi_clk SCMI_CLK_NPU>;
assigned-clock-rates =3D <200000000>;
```

The initial rate is set to 200 MHz here, but the driver's `rk3568_noc_init(=
)` immediately ramps it to 600 MHz then 1 GHz. Consider whether 200 MHz is =
the right boot-time default, or whether the `assigned-clock-rates` should m=
atch the target operational frequency.

**4. Otherwise clean**

The node structure (reg regions, clocks, resets, power domain, IOMMU refere=
nce) mirrors the RK3588 pattern appropriately. The `rockchip,pmu =3D <&pmu>=
` phandle is present as required by the driver.

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