From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/rockchip: dsi: Relax the lane rate margin requirements Date: Thu, 04 Jun 2026 11:57:42 +1000 Message-ID: In-Reply-To: <20260603033532.164-4-kernel@airkyi.com> References: <20260603033532.164-1-kernel@airkyi.com> <20260603033532.164-4-kernel@airkyi.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Patch Review **Status: Looks correct, accept with caveats** Changes the overhead factor from `10/8` (25% margin, i.e. 1/0.8) to `10/9` = (~11% margin, i.e. 1/0.9) in two places: ```c /* Internal PHY path */ tmp =3D mpclk * (bpp / lanes) * 10 / 9; /* External PHY path */ phy_mipi_dphy_get_default_config(mode->clock * 1000 * 10 / 9, bpp, lanes, &dsi->phy_opts.mipi_dphy); ``` The commit message gives a concrete justification: RGB888 at 148.5 MHz with= 4 lanes at 1/0.8 overhead =3D 1113.75 Mbps, which exceeds the 1000 Mbps li= mit on PX30/RK3128/RV1126. With 1/0.9, it becomes ~990 Mbps, which fits. **Concerns:** - The MIPI DSI spec recommends that the data rate should exceed the require= d bandwidth to account for protocol overhead (LP escape, ECC, CRC, etc.). 1= 1% margin is tighter than typical. The commit message says "downstream test= results" validate this, but it would be helpful to know on which panels/So= Cs this was tested. - The comment `/* since mbps must big than bandwidth of RGB */` (grammar as= ide) is retained but the meaning changes =E2=80=94 the margin is now signif= icantly tighter. - This is ordered as patch 3/3, so it depends on patch 1 having already set= the correct per-chip max. The combination works: chips limited to 1000 Mbp= s can now drive 148.5 MHz RGB888 panels, which was the motivating use case. --- ## SUMMARY | Patch | Verdict | |-------|---------| | 1/3 =E2=80=94 max lane bit rate | **OK** | | 2/3 =E2=80=94 dphy_get_timing | **BUG: rk3506_chip_data missing `.dphy_ge= t_timing` =E2=80=94 will NULL deref** | | 3/3 =E2=80=94 relax margin | **OK with caveat** (tighter margin; needs te= sted panel coverage noted) | The series should not be merged until `rk3506_chip_data` gets its `.dphy_ge= t_timing` assignment added (likely `dw_mipi_dsi_phy_px30_get_timing`). --- Generated by Claude Code Patch Reviewer