From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: clk: renesas: r9a09g047: Add CLK_PLLDSI{0,1} clocks Date: Sun, 12 Apr 2026 12:45:56 +1000 Message-ID: In-Reply-To: References: X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Patch Review Adds PLLDSI0 and PLLDSI1 PLL definitions and their frequency limits in `include/linux/clk/renesas.h`. **Observation**: The DSI0 and DSI1 limits differ only in `fout.max` (1218 MHz vs 609 MHz). All other parameters are identical. This could be a single macro parameterized by `fout_max`, but the current approach with two separate macros is clear and matches existing patterns in the file. No issues. Has Reviewed-by from Geert. --- Generated by Claude Code Patch Reviewer