Claude review: drm: renesas: rz-du: Add RZ/G3E support

Claude Code Review Bot
2026-04-12T02:45:59Z

Patch Review

Adds the DU driver support for RZ/G3E with SMUX2 clock mux selection via duty cycle.

**Issue (design - duty cycle at wrong level)**: In `rzg2l_du_crtc_set_display_timing()`:

```c
if (rzg2l_du_has(rcdu, RZG2L_DU_FEATURE_SMUX2_DSI_CLK)) {
struct clk *clk_parent;

clk_parent = clk_get_parent(rcrtc->rzg2l_clocks.dclk);
...
if (rstate->outputs == BIT(RZG2L_DU_OUTPUT_LVDS0) ||
rstate->outputs == BIT(RZG2L_DU_OUTPUT_LVDS1))
clk_set_duty_cycle(clk_parent, 4, 7);
else
clk_set_duty_cycle(clk_parent, 1, 2);
}
```

The code gets the parent of `dclk` and sets the duty cycle on it. This means the DU driver needs to know about the clock tree internals (that the parent is a SMUX clock that uses duty cycle to select paths). This is a layering violation. If the clock tree ever changes, this DU code would break. However, this appears to be a conscious design choice discussed in earlier review rounds.

**The `clk_parent` is not released**: `clk_get_parent()` returns a `struct clk *`. The kernel's `clk_get_parent()` does not increment the refcount so no `clk_put` is needed — this is correct.

**Observation**: The `rzg2l_du_crtc_atomic_check()` function iterates over encoders to determine output routes, matching the rcar DU pattern. This is clean.

**Minor**: The `rzg2l_du_r9a09g047_du_info` only defines `channels_mask = BIT(0)` (single channel). Since the SoC has two DU instances (DU0, DU1), each DU node in DTS will probe as a separate device with its own single channel. This is correct.

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