From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/panfrost: Add GPU_PM_RT support for RZ/G3L SoC Date: Thu, 05 Mar 2026 13:22:27 +1000 Message-ID: In-Reply-To: <20260304134845.267030-5-biju.das.jz@bp.renesas.com> References: <20260304134845.267030-1-biju.das.jz@bp.renesas.com> <20260304134845.267030-5-biju.das.jz@bp.renesas.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Patch Review This patch adds a single compatible entry `renesas,r9a08g046-mali` pointing= to `default_pm_rt_data`. **Looks correct.** The placement is alphabetically ordered next to the exis= ting `r9a09g047` entry. The `default_pm_rt_data` provides `GPU_PM_RT` which= ensures the reset assert/deassert and clock enable/disable happen during r= untime suspend/resume, matching the cover letter's description. **Minor: The commit message says "RZ/G3L SoC" but doesn't mention which GPU= it has.** The cover letter states it's a Mali-G31, and this is a bifrost d= river entry, so it's fine, but the commit message could be slightly more de= scriptive. --- **Summary of required changes:** 1. **Patch 3**: Remove the duplicate `err =3D PTR_ERR(pfdev->bus_ace_clock)= ` assignment =E2=80=94 this is a clear copy-paste bug. **Optional improvements:** - **Patch 3**: Harmonize the `bus_clock` init code with the `bus_ace_clock`= init code (either both guarded or both unguarded for `clk_prepare_enable`). --- Generated by Claude Code Patch Reviewer