From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/msm/adreno: Trust the SSoT UBWC config Date: Mon, 09 Mar 2026 08:32:15 +1000 Message-ID: In-Reply-To: <20260306-ubwc-rework-v1-4-9cfdff12f2bb@oss.qualcomm.com> References: <20260306-ubwc-rework-v1-0-9cfdff12f2bb@oss.qualcomm.com> <20260306-ubwc-rework-v1-4-9cfdff12f2bb@oss.qualcomm.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Patch Review >From Konrad Dybcio. Removes the entire `a6xx_calc_ubwc_config()` function which had per-GPU hardcoded `highest_bank_bit` and `ubwc_swizzle` overrides, and drops the `_ubwc_config` mutable copy: ```c - /* Copy the data into the internal struct to drop the const qualifier (temporarily) */ - *cfg = *common_cfg; - - /* Use common config as is for A8x */ - if (!adreno_is_a8xx(gpu)) { - cfg->ubwc_swizzle = 0x6; - cfg->highest_bank_bit = 15; - } ``` This is a significant simplification that trusts the central UBWC config database. The removed `DRM_WARN_ONCE` for mismatched values was previously useful for validation but is no longer needed if the database is authoritative. Good cleanup. Has appropriate R-b tags. --- Generated by Claude Code Patch Reviewer